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*optimized pcb layout gerber files downloadable from the enpirion website to assure first pass design success. EP5352Q/ep5362q/ep5382q 500/600/800ma synchrono us buck regulators with integrated inductor rohs compliant voltage select dac switch vref (+) (-) error amp v sense v fb v out vs0 vs1 vs2 package boundry p-drive n-drive uvlo thermal limit current limit soft start sawtooth generator (+) (-) pwm comp v in enable gnd logic compensation network product highlights ? revolutionary integrated inductor ? very small solution foot print* ? fully rohs compliant; msl 3 260c reflow ? only two low cost components required ? 5mm x 4mm x1.1mm qfn package ? wide 2.4v to 5.5v input range ? 500, 600, 800 ma ou tput current versions ? less than 1 a standby current ? 4 mhz switch ing frequency ? fast transient response ? very low ripple voltage; 5mv p-p typical ? 3 pin vid output voltage select ? external divider option ? dynamically adjustable output ? designed for low noise/emi ? short circuit, uvlo, and thermal protection product overview the ultra-low-profile ep53x 2q product family is targeted to applications where board area and profile are critical. ep53 x2q is a complete power conversion solution requiring only two low cost ceramic mlcc caps. inductor, mosfets, pwm, and compensation are integrated into a tiny 5mm x 4mm x 1.1 mm qfn package. the ep53x2q family is engineered to simplify design and to minimize layout constraints. high switching frequency and internal type iii compensation provides superior transient response. with a 1.1 mm profile, the ep53x2 is perfect for space and height limited applications. a 3-pin vid output voltage select scheme provides seven pre-progr ammed output voltages along with an option for extern al resistor divider. output voltage can be programmed on-the-fly to provide fast, dynamic voltage scaling. typical application circuit v in v sense v in v s1 v s2 v s0 10 f 2.2uf v out v out gnd enable v fb voltage select figure 1. typical application circuit. applications ? area constrained applications ? mobile multimedia, smartphone & pda ? mobile and cellular platforms ? voip and video phones ? personal media players ? fpga, dsp, io & peripherals 03132 4/28/2009 rev:b www.datasheet.in
ep5382q/ep5362q/EP5352Q ? enpirion 2009 all rights reserved, e&oe 2 www.enpirion.com absolute maximum ratings caution: absolute maximum ratings are stress ratings only. functional operation beyond recommended operating conditions is not implied. stress beyond absolute ma ximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions fo r extended periods may affect device reliability. parameter symbol min max units input supply voltage v in -0.3 7.0 v voltages on: enable, v sense , v s0 -v s2 -0.3 v in + 0.3 v voltage on: v fb -0.3 2.7 v storage temperature range t stg -65 150 c reflow temp, 10 sec, msl3 jedec j-std-020a 260 c esd rating (based on human body model) 2000 v recommended operating conditions parameter symbol min max units input voltage range v in 2.4 5.5 v output voltage range v out 0.6 v in -0.45 v operating ambient temperature t a -40 +85 c operating junction temperature t j -40 +125 c thermal characteristics parameter symbol typ units thermal resistance: junction to ambient (0 lfm) ja 65 c/w thermal resistance: junction to case (0 lfm) jc 15 c/w thermal shutdown t j-tp +150 c thermal shutdown hysteresis 15 c electrical characteristics note: t a = 25c unless otherwise noted. typi cal values are at vin = 3.6v. EP5352Qi, ep5362qi: c in = 2.2 f, c out =10uf. ep5382qi: c in = 4.7 f, c out =10uf. parameter symbol test conditions min typ max units operating input voltage v in 2.4 5.5 v under voltage lockout v uvlo vin going low to high 2.2 2.3 v uvlo hysteresis 0.145 v v out initial accuracy v out 2.4v v in 5.5v, i load = 100ma; t a = 25c -2.0 +2.0 % v out variation for all causes v out 2.4v v in 5.5v, i load = 0 - 1a, t a = -40c to +85c -3.0 +3.0 % feedback pin voltage v fb 2.4v v in 5.5v, i load = 100ma vso=vs1=vs2=1 0.591 0.603 0.615 v feedback pin input current i fb 1 na feedback pin voltage v fb 2.4v v in 5.5v, i load = 0-800ma, t a = -40c to +85c vso=vs1=vs2=1 0.585 0.603 0.621 v dynamic voltage slew rate v slew 3 mv/ s 03132 4/28/2009 rev:b www.datasheet.in
ep5382q/ep5362q/EP5352Q ? enpirion 2009 all rights reserved, e&oe 3 www.enpirion.com parameter symbol test conditions min typ max units continuous output current EP5352Qi i out EP5352Q 500 ma continuous output current ep5362qi i out ep5362q 600 ma continuous output current ep5382qi i out ep5382q 800 ma shut-down current i sd enable = low 0.75 a quiescent current no switching 800 a pfet ocp threshold i lim 2.4v v in 5.5v, 0.6v v out v in ? 0.6v 1.4 2 a vs0-vs1 voltage threshold pin = low pin = high 0.0 1.4 0.4 v in v vs0-vs2 pin input current i vsx 1 na enable voltage threshold logic low logic high 0.0 1.4 0.2 v in v enable pin input current i en v in = 3.6v 2 a operating frequency f osc 4 mhz pfet on resistance r ds(on) 340 m nfet on resistance r ds(on) 270 m internal inductor dcr .110 soft-start operation time to 90% v out t ss vout = 3.3v 1 ms 03132 4/28/2009 rev:b www.datasheet.in
ep5382q/ep5362q/EP5352Q ? enpirion 2009 all rights reserved, e&oe 4 www.enpirion.com pin description v in (pin 1,2): input volt age pin. supplies power to the ic. v in can range from 2.4v to 5.5v. input gnd : (pin 3): input power ground. connect this pin to the ground terminal of the input capacitor. refer to layout recommendations for further details. output gnd : (pin 4): power ground. the output filter capacitor should be connected to this pin. refer to layout recommendations for further detail. v out (pin 5,6,7): regulated output voltage. nc (pin 8,9,10,11,12, 13,14): these pins should not be electrically connected to each other or to any external signal, voltage, or ground. one or more of these pins may be connected internally. v sense (pin 15): sense pin for output voltage regulation. connect v sense to the output voltage rail as close to the terminal of the output filter capacitor as possible. v fb (pin 16): feed back pin for external divider option. when using the ex ternal divider option (vs0=vs1=vs2= high) connect this pin to the center of the external divider. set the divider such that v fb = 0.603v. vs0,vs1,vs2 (pin 17,18,19): output voltage select. vs0=pin19, vs1=pin18, vs2=pin17. selects one of seven pr eset output voltages or choose external divider by connecting pins to logic high or low. logic low is defined as v low 0.4v. logic hi gh is defined as v high 1.4v. any level between these two values is indeterminate. (refer to section on output voltage select for more detail). enable (pin 20): output enable. enable = logic high, disable = logic low. logic low is defined as v low 0.2v. logic high is defined as v high 1.4v. any level between these two values is indeterminate. thermal pad. thermal pad to remove heat from package. connect to surface ground pad and pcb internal ground plane. figure 2. pin description, top view. v out nc nc nc v out v fb v sense nc nc nc nc v out gnd gnd v in enable vs0 vs1 vs2 1 2 6 5 4 3 10 9 8 7 11 12 13 14 15 16 20 19 18 17 v in v out nc nc nc v out v fb v sense nc nc nc nc v out gnd gnd v in enable vs0 vs1 vs2 1 2 5 4 3 10 9 8 7 11 12 13 14 15 16 20 19 18 17 v in thermal pad 6 figure 3. pin description, bottom view. 03132 4/28/2009 rev:b www.datasheet.in
ep5382q/ep5362q/EP5352Q ? enpirion 2009 all rights reserved, e&oe 5 www.enpirion.com functional block diagram voltage select dac switch vref (+) (-) error amp v sense v fb v out vs0 vs1 vs2 package boundry p-drive n-drive uvlo thermal limit current limit soft start sawtooth generator (+) (-) pwm comp v in enable gnd logic compensation network figure 4. functional block diagram. 03132 4/28/2009 rev:b www.datasheet.in
ep5382q/ep5362q/EP5352Q ? enpirion 2009 all rights reserved, e&oe 6 www.enpirion.com typical performance characteristics 50 55 60 65 70 75 80 85 90 95 50 150 250 350 450 550 efficiency vs output current v out = 3.3v load current (ma) v in = 5.0v v out = 3.0v v out = 2.7v v out = 2.5v v out = 1.8v efficiency -% 50 55 60 65 70 75 80 85 90 95 50 150 250 350 450 550 efficiency vs output current v out = 3.3v load current (ma) v in = 5.0v v out = 3.0v v out = 2.7v v out = 2.5v v out = 1.8v efficiency -% 50 55 60 65 70 75 80 85 90 95 100 50 150 250 350 450 550 efficiency vs output current v out = 1.2v load current (ma) v in = 3.3v v out = 3.0v v out = 2.7v v out = 2.5v v out = 1.8v efficiency -% 50 55 60 65 70 75 80 85 90 95 100 50 150 250 350 450 550 efficiency vs output current v out = 1.2v load current (ma) v in = 3.3v v out = 3.0v v out = 2.7v v out = 2.5v v out = 1.8v efficiency -% transient response v out 50mv/div i load 500ma/div v in = 5.0v v out = 3.3v i load = 100ma to 800ma 20 s/div transient response v out 50mv/div i load 500ma/div v in = 5.0v v out = 3.3v i load = 100ma to 800ma 20 s/div transient response v out 50mv/div i load 500ma/div v in = 3.3v v out = 1.8v i load = 100ma to 800ma 20 s/div transient response v out 50mv/div i load 500ma/div v in = 3.3v v out = 1.8v i load = 100ma to 800ma 20 s/div 50 55 60 65 70 75 80 85 90 95 100 50 150 250 350 450 550 efficiency vs output current v out = 3.3v load current (ma) v in = 3.6v v out = 3.0v v out = 2.7v v out = 2.5v v out = 1.8v efficiency -% 50 55 60 65 70 75 80 85 90 95 100 50 150 250 350 450 550 efficiency vs output current v out = 3.3v load current (ma) v in = 3.6v v out = 3.0v v out = 2.7v v out = 2.5v v out = 1.8v efficiency -% start up waveform v out 1v/div enable 2v/div v in = 5.0v v out = 3.3v 200 s/div start up waveform v out 1v/div enable 2v/div v in = 5.0v v out = 3.3v 200 s/div output ripple v out 10mv/div v in = 3.6v v out = 3.3v output cap = 2 x 10 f 0805 200ns/div output ripple v out 10mv/div v in = 3.6v v out = 3.3v output cap = 2 x 10 f 0805 200ns/div output ripple v out 10mv/div v in = 3.6v v out = 3.3v output cap = 10 f 0805 200ns/div output ripple v out 10mv/div v in = 3.6v v out = 3.3v output cap = 10 f 0805 200ns/div 03132 4/28/2009 rev:b www.datasheet.in
ep5382q/ep5362q/EP5352Q ? enpirion 2009 all rights reserved, e&oe 7 www.enpirion.com detailed description functional overview the ep53x2q family is a complete dcdc converter solution requiri ng only two low cost mlcc capacitors. mosfet switches, pwm controller, gate-drive, compensation, and inductor are integrated into the tiny 5mm x 4mm x 1.1mm package to provide the smallest footprint possible wh ile maintaining high efficiency and high performance. the converter uses voltage mode control to provide the simplest implementation and high noise immunity. the device operates at a 4 mhz switching frequency. the high switching frequency allows for a wide control loop bandwidth providing excellent transient performance. the 4 mhz switching frequency enables the use of very small components making possible this unprecedented level of integration. enpirion?s proprietary power mosfet technology provides very low switching loss at frequencies of 4 mhz and higher, allowing for the use of very small internal components, and very wide control loop bandwidth. unique magnetic design allows fo r integration of the inductor into the very low profile 1.1mm package. integration of the inductor virtually eliminates the design/ layout issues normally associated with switch-mode dcdc converters. all of this enables much easier and faster integration in to various applications to meet demanding emi requirements. output voltage is chosen from seven preset values via a three pi n vid voltage select scheme. an external divider option enables the selection of any vo ltage in the 0.6 to v in - v dropout . this reduces the number of components that must be qualified and reduces inventory problem s. the vid pins can be toggled on the fly to implement glitch free dynamic voltage scaling. protection features in clude under-voltage lock- out (uvlo), over-current protection (ocp), short circuit protection, and thermal overload protection. integrated inductor enpirion has introduc ed the world?s first product family featuring integrated inductors. the ep53x2q family utilizes a low loss, planar construction inductor. the use of an internal inductor localizes the noises associated with the output loop currents. the inherent shielding and compact construction of the integrated inductor reduces the radiated noise that couples into the traces of the circuit board. further, the package layo ut is optimized to reduce the electrical path length for the ac ripple currents that are a major source of radiated emissions from dcdc converters. the integrated inductor significantly reduces parasitic effects that can harm loop stability, and makes layout very simple. soft start internal soft start circuits limit in-rush current when the device starts up from a power down condition or when the ?enable? pin is asserted ?high?. digital control circuitry limits the v out ramp rate to levels that are safe for the power mosfets and the integrated inductor. the soft start ramp rate is nominally 3.3mv/ sec. over current/short circuit protection the current limit function is achieved by sensing the current flowing through a sense p- mosfet which is compared to a reference current. when this level is exceeded the p- fet is turned off and the n-fet is turned on, pulling v out low. this condition is maintained for a period of 1ms and then a normal soft start is initiated. if the ov er current condition still persists, this cycle will repeat in a ?hiccup? mode. 03132 4/28/2009 rev:b www.datasheet.in
ep5382q/ep5362q/EP5352Q ? enpirion 2009 all rights reserved, e&oe 8 www.enpirion.com under voltage lockout during initial power up an under voltage lockout circuit will hold-off the switching circuitry until the in put voltage reaches a sufficient level to insure proper operation. if the voltage drops below the uvlo threshold the lockout circuitry will again disable the switching. hysteresis is included to prevent chattering between states. enable the enable pin provides a means to shut down the converter or enable normal operation. a logic low wil l disable the converter and cause it to shut down. a logic high will enable the converter into normal operation. in shutdown mode, the devic e quiescent current will be less than 1 ua. the enable pin must not be left floating. thermal shutdown when excessive power is dissipated in the chip, the junction temperature rises. once the junction temperature exceeds the thermal shutdown temperature t he thermal shutdown circuit turns off the co nverter output voltage thus allowing the device to cool. when the junction temperature decreases by 15c , the device will go through the normal startup process. application information output voltage select to provide the highest degree of flexibility in choosing output voltage, the ep53x2q family uses a 3 pin vid, or voltage id, output voltage select arrangement. this allows the designer to choose one of seven preset voltages, or to use an external voltage di vider. internally, the output of the vid multiplexer sets the value for the voltage reference dac, which in turn is connected to the non-inverting input of the error amplifier. this allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. table 1 shows the vari ous vs0-vs2 pin logic states and the associated output voltage levels. a logic ?1? in dicates a connection to v in or to a ?high? logic voltage level. a logic ?0? indicates a connection to ground or to a ?low? logic voltage level. these pins can be either hardwired to v in or gnd or alternatively can be driven by standard logic levels. logic low is defined as v low 0.4v. logic high is defined as v high 1.4v. any level between these two values is indeterminate. these pins must not be left floating. vs2 vs1 vs0 v out 0 0 0 3.3 0 0 1 2.5 0 1 0 2.8 0 1 1 1.2 1 0 0 3.0 1 0 1 1.8 1 1 0 2.7 1 1 1 external external voltage divider as described above, the external voltage divider option is chosen by connecting the vs0, vs1, and vs2 pins to v in or logic ?high?. the ep53x2q uses a separate feedback pin, v fb , when using the external divider. vsense must be connected to v out as indicated in figure 5. table 1. voltage select settings. 03132 4/28/2009 rev:b www.datasheet.in
ep5382q/ep5362q/EP5352Q ? enpirion 2009 all rights reserved, e&oe 9 www.enpirion.com v in v sense v in v s1 v s2 v s0 10 f 2.2uf 4.7uf v out v out gnd enable ra rb v fb figure 5. external divider. the output voltage is selected by the following formula: ( ) rb ra out v v + = 1603.0 r a must be chosen as 200k to maintain loop gain. then r b is given as: ? = 603.0 102.1 5 out b v x r dynamically adjustable output the ep53x2q are designed to allow for dynamic switching be tween the predefined vid voltage levels the inter-voltage slew rate is optimized to prevent excess undershoot or overshoot as the output voltage levels transition. the slew rate is identical to the soft- start slew rate of 3.3mv/us. dynamic transitioning between internal vid settings and the external divider is not allowed. input and output capacitors the input capacitance requirement is as follows: EP5352Q, ep5362q = 2.2uf ep5382q = 4.7uf enpirion recommends that a low esr mlcc capacitor be used. t he input capacitor must use a x5r or x7r or equivalent dielectric formulation. y5v or equivalent dielectric formulations lose capacitance with frequency, bias, and with temperature, and are not suitable for switch-mode dc-dc converter input and output filter applications. the output capacitance requirement is a minimum of 10uf. the control loop is designed to be stable wit h up to 60uf of total output capacitance without requiring modification of the control loop. capacitance above the 10uf minimum should be added if the transient performance is not sufficient using the 10uf. enpirion recommends a low esr mlcc type capacitor be used. the output capacitor must use a x5r or x7r or equivalent dielectric formulation. y5v or equivalent dielectric formulation s lose capacitance with frequency, bias, and tem perature and are not suitable for switch-mode dc-dc converter input and output filt er applications. cin manufacturer part # v alue wvdc case size murata grm219r61a475ke19d 4.7uf 10v 0805 grm319r61a475ka01d 1206 grm219r60j475ke01d 6.3v 0805 grm31mr60j475ka01l 1206 panasonic ecj-2fb1a475k 10v 0805 ecj-3yb1a475k 1206 ecj-2fb0j475k 6.3v 0805 ecj-3yb0j475k 1206 taiyo yuden lmk212bj475kg-t 10v 0805 lmk316bj475kd-t 1206 jmk212bj475kd-t 6.3v 0805 cou t manufacture r part # v alue wvdc case size murata grm219r60j106ke19d 10uf 6.3v 0805 grm319r60j106ke01d 1206 panasonic ecj-2fb0j106k 6.3v 0805 ecj-3yb0j106k 1206 taiyo yuden jmk212bj106kd-t 6.3v 0805 jmk316bj106kf-t 1206 cin manufacturer part # v alue wvdc case size murata grm21br71a225ka01l 2.2uf 10v 0805 grm31mr71a225ka01l 1206 grm21br70j225ka01l 6.3v 0805 panasonic ecj-2fb1a225k 10v 0805 ecj-3yb1a225k 1206 ecj-2yb0j225k 6.3v 0805 taiyo yuden lmk107bj225ka-t 10v 0603 lmk212bj225kg-t 0805 03132 4/28/2009 rev:b www.datasheet.in
ep5382q/ep5362q/EP5352Q ? enpirion 2009 all rights reserved, e&oe 10 www.enpirion.com layout considerations* *optimized pcb layout file downloadable from the enpi rion website to assure first pass design success recommendation 1: input and output f ilter capacitors should be pl aced as close to the ep53x2qi package as possible to reduce emi from input and output loop ac currents. this reduces the physical area of the input and output ac current loops. recommendation 2: do not connect gnd pins 3 and 4 toge ther. pin 3 should be used for the input capacitor local ground and pi n 4 should be used for the output capacitor ground. the ground pad for the input and output filt er capacitors should be isolated ground islands and should be connected to system ground as indicated in recommendation 3 and recommendation 5. recommendation 3: multiple small vias (0.25mm after c opper plating) should be used to connect ground terminals of the input capacit or and the output capacitor to the system ground plane. this provides a low inductance path for the high-frequen cy ac currents, thereby reducing ripple and suppressing emi (see fig. 5, fig. 6, and fig. 7). recommendation 4: the large thermal pad underneath the co mponent must be connected to the system ground plane through as many thermal vias as possible. the vias should use 0.33mm drill size with minimum one ounce copper plating (0.035mm plating thickness) . this provides the path for heat dissipation from the converter. recommendation 5: the system ground plane referred to in recommendations 3 and 4 should be the first layer immediately below the surface layer (pcb layer 2). this ground plane should be continuous and un-interrupted below the converter and the input and output capacitors that carry large ac currents. if it is not possible to make pcb layer 2 a continuous ground plane, an uninterrupted ground ?island? should be created on pcb laye r 2 immediately underneath the en5312qi and its input and output capac itors. the vias that connect the input and output capacitor grounds, and the thermal pad to the ground island, shoul d continue through to the pcb gnd layer as well. recommendation 6 : as with any switch-mode dc/dc converte r, do not run sensitive signal or control lines underneath the converter package. figure 6 shows an example schematic for the ep53x2q using the internal voltage select. in this example, the device is set to a v out of 1.2v (vs2=0, vs1=1, vs0=1). 03132 4/28/2009 rev:b www.datasheet.in
ep5382q/ep5362q/EP5352Q ? enpirion 2009 all rights reserved, e&oe 11 www.enpirion.com v out nc nc nc v out v fb v sense nc nc nc nc v out gnd gnd v in enable vs0 vs1 vs2 1 2 6 5 4 3 10 9 8 7 11 12 13 14 15 16 20 19 18 17 v in agnd 4.7uf/2.2uf 10 f v in v out (see layout recommendation 3) figure 6. example application, vout=1.2v. figure 7 shows an example schematic using an exter nal voltage divider. vs0=vs1=vs2= ?1?. the resistor values are chosen to give an output voltage of 2.6v. v out nc nc nc v out v fb v sense nc nc nc nc v out gnd gnd v in enable vs0 vs1 vs2 1 2 6 5 4 3 10 9 8 7 11 12 13 14 15 16 20 19 18 17 v in agnd 4.7uf 10 f v in v out ra=200k rb=60k (see layout recommendation 3) figure 7. schematic showing the use of external divider option, vout = 2.6v. figure 8 shows two example board layouts. note t he placement of the input and output capacitors. they are placed close to the device to minimize t he physical area of the ac current loops. note the placement of the vias per recommendation 3. 03132 4/28/2009 rev:b www.datasheet.in
ep5382q/ep5362q/EP5352Q ? enpirion 2009 all rights reserved, e&oe 12 www.enpirion.com vias to ground plane thermal vias to ground plane vias to ground plane thermal vias to ground plane figure 8. example layout showing pcb top layer, as well as demonstrating use of vias from input, output filter capacitor local grounds, and thermal pad, to pcb system ground. design considerations for lead-frame based modules exposed metal on bottom of package enpirion has developed a break-through in package technol ogy that utilizes the lead frame as part of the electrical circuit. the lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. however, it doe s require some special considerations. as part of the package assembly process, lead frame construction requir es that for mechanical support, some of the lead-frame me tal be exposed at the point wher e wire-bond or internal passives are attached. this results in several sma ll pads being exposed on the bottom of the package. only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to the pc board. the pcb top layer under the ep53x2 qi should be clear of any metal except for the large thermal pad. the ?grayed-out? area in figure 9 represents the area that should be clear of any metal (traces, vias, or planes), on the top laye r of the pcb. note: clearance between the various exposed me tal pads, the thermal ground pad, and the perimeter pins, meets or exceeds jedec requirements for lead frame package construction (jedec mo-220, issue j, date may 2005). the separat ion between the large t hermal pad and the nearest adjacent metal pad or pin is a minimum of 0.20mm, in cluding tolerances. this is shown in figure 10. c in package outline c out c in package outline c out 03132 4/28/2009 rev:b www.datasheet.in
ep5382q/ep5362q/EP5352Q ? enpirion 2009 all rights reserved, e&oe 13 www.enpirion.com figure 9. exposed metal and mechanical dimensions of t he package . gray area represents bottom metal no-connect and area that should be clear of any traces, plane s, or vias, on the top layer of the pcb. 0.25 0.20 0.20 0.20 0.25 jedec minimum separation = 0.20 0.25 0.20 0.20 0.20 0.25 jedec minimum separation = 0.20 figure 10. exposed pad clearances; the enpirion lead frame package complies with jedec requirements. thermal pad. connect to ground plane 03132 4/28/2009 rev:b www.datasheet.in
ep5382q/ep5362q/EP5352Q ? enpirion 2009 all rights reserved, e&oe 14 www.enpirion.com figure 11. recommended pcb solder mask openings. 03132 4/28/2009 rev:b www.datasheet.in
ep5382q/ep5362q/EP5352Q ? enpirion 2009 all rights reserved, e&oe 15 www.enpirion.com figure 12. package mechanical dimensions. 03132 4/28/2009 rev:b www.datasheet.in
ep5382q/ep5362q/EP5352Q ? enpirion 2009 all rights reserved, e&oe 16 www.enpirion.com contact information enpirion, inc. 685 us route 202/206 suite 305 bridgewater, nj 08807 phone: 908-575-7550 fax: 908-575-0775 enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. information fur nished by enpirion is believed to be accurate and reliable. enpirion assumes no responsi bility for its use or for infringement of patents or other th ird party rights, which may result from its use. enpirion products are not authorized for use in nuclear control systems, as critical components in life su pport systems or equipment used in hazardous environment without the ex press written authority from enpirion. 03132 4/28/2009 rev:b www.datasheet.in

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